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| 8 Bit Microcontroller TLCS-870/C Series TMP86CH21AUG TMP86CH21AUG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2006 TOSHIBA CORPORATION All Rights Reserved Page 2 Revision History Date 2006/1/31 2006/7/10 2006/7/27 2006/9/4 2006/9/5 Revision 1 2 3 4 5 First Release Periodical updating.No change in contents. Periodical updating.No change in contents. Contents Revised Contents Revised Table of Contents TMP86CH21AUG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory Address Map............................................................................................................................... 9 Program Memory (MaskROM).................................................................................................................. 9 Data Memory (RAM) ................................................................................................................................. 9 Clock Generator...................................................................................................................................... 10 Timing Generator .................................................................................................................................... 12 Operation Mode Control Circuit .............................................................................................................. 13 Single-clock mode Dual-clock mode STOP mode Configuration of timing generator Machine cycle 2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 2.2.2.1 2.2.2.2 2.2.3.1 2.2.3.2 2.2.3.3 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4 Operating Mode Control ......................................................................................................................... 18 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 External Reset Input ............................................................................................................................... 31 Address trap reset .................................................................................................................................. 32 Watchdog timer reset.............................................................................................................................. 32 System clock reset.................................................................................................................................. 32 2.3.1 2.3.2 2.3.3 2.3.4 3. Interrupt Control Circuit 3.1 3.2 3.3 3.4 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Interrupt acceptance processing is packaged as follows........................................................................ 39 Saving/restoring general-purpose registers ............................................................................................ 40 Interrupt return ........................................................................................................................................ 42 Using PUSH and POP instructions Using data transfer instructions 3.2.1 3.2.2 Interrupt master enable flag (IMF) .......................................................................................................... 36 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 36 3.4.1 3.4.2 3.4.3 3.5.1 3.5.2 3.4.2.1 3.4.2.2 3.5 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Address error detection .......................................................................................................................... 43 Debugging .............................................................................................................................................. 43 i 3.6 3.7 3.8 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 4. Special Function Register (SFR) 4.1 4.2 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 DBR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 5.6 Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P33 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P5 (P57 to P50) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P6 (P67 to P60) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P7 (P77 to P70) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 53 54 55 56 58 6. Time Base Timer (TBT) 6.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59 Configuration .......................................................................................................................................... 59 Control .................................................................................................................................................... 59 Function .................................................................................................................................................. 60 Configuration .......................................................................................................................................... 61 Control .................................................................................................................................................... 61 6.1.1 6.1.2 6.1.3 6.2.1 6.2.2 6.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 7. Watchdog Timer (WDT) 7.1 7.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 64 65 66 66 67 7.3 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 68 68 68 69 7.3.1 7.3.2 7.3.3 7.3.4 8. 18-Bit Timer/Counter (TC1) 8.1 8.2 8.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Timer mode............................................................................................................................................. 75 8.3.1 ii 8.3.2 8.3.3 8.3.4 Event Counter mode ............................................................................................................................... 76 Pulse Width Measurement mode............................................................................................................ 77 Frequency Measurement mode .............................................................................................................. 78 9. 8-Bit TimerCounter (TC3, TC4) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 8-Bit Timer Mode (TC3 and 4) ................................................................................................................ 8-Bit Event Counter Mode (TC3, 4) ........................................................................................................ 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)..................................................................... 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4).................................................................. 16-Bit Timer Mode (TC3 and 4) .............................................................................................................. 16-Bit Event Counter Mode (TC3 and 4) ................................................................................................ 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4).......................................................... 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ............................................... Warm-Up Counter Mode......................................................................................................................... Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 9.3.1 9.3.2 9.3.3 9.3.4 9.3.5 9.3.6 9.3.7 9.3.8 9.3.9 87 88 88 91 93 94 94 97 99 9.3.9.1 9.3.9.2 10. 8-Bit TimerCounter (TC5, TC6) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 8-Bit Timer Mode (TC5 and 6) ............................................................................................................ 8-Bit Event Counter Mode (TC6) ........................................................................................................ 8-Bit Programmable Divider Output (PDO) Mode (TC6)..................................................................... 8-Bit Pulse Width Modulation (PWM) Output Mode (TC6).................................................................. 16-Bit Timer Mode (TC5 and 6) .......................................................................................................... 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6)...................................................... 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) ........................................... Warm-Up Counter Mode..................................................................................................................... Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 10.3.1 10.3.2 10.3.3 10.3.4 10.3.5 10.3.6 10.3.7 10.3.8 106 107 107 110 112 113 116 118 10.3.8.1 10.3.8.2 11. Synchronous Serial Interface (SIO) 11.1 11.2 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122 Serial clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 Clock source ....................................................................................................................................... 123 Shift edge............................................................................................................................................ 125 Leading edge Trailing edge Internal clock External clock 11.3.1.1 11.3.1.2 11.3.2.1 11.3.2.2 11.3.1 11.3.2 11.4 11.5 11.6 Number of bits to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Number of words to transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125 Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 4-bit and 8-bit transfer modes ............................................................................................................. 126 4-bit and 8-bit receive modes ............................................................................................................. 128 8-bit transfer / receive mode ............................................................................................................... 129 11.6.1 11.6.2 11.6.3 iii 12. Asynchronous Serial interface (UART ) 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer Rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . STOP Bit Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Parity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Transmit Operation .................................................................................................................... 136 Data Receive Operation ..................................................................................................................... 136 137 137 137 138 138 139 131 132 134 135 135 136 136 136 12.8.1 12.8.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Parity Error.......................................................................................................................................... Framing Error...................................................................................................................................... Overrun Error ...................................................................................................................................... Receive Data Buffer Full..................................................................................................................... Transmit Data Buffer Empty ............................................................................................................... Transmit End Flag .............................................................................................................................. 12.9.1 12.9.2 12.9.3 12.9.4 12.9.5 12.9.6 13. 8-Bit AD Converter (ADC) 13.1 13.2 13.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144 AD Conveter Operation ...................................................................................................................... AD Converter Operation ..................................................................................................................... STOP and SLOW Mode during AD Conversion ................................................................................. Analog Input Voltage and AD Conversion Result ............................................................................... 144 144 145 146 13.4 13.3.1 13.3.2 13.3.3 13.3.4 13.4.1 13.4.2 13.4.3 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 147 Analog input pin voltage range ........................................................................................................... 147 Analog input shared pins .................................................................................................................... 147 Noise countermeasure........................................................................................................................ 147 14. Key-on Wakeup (KWU) 14.1 14.2 14.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 15. LCD Driver 15.1 15.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 152 LCD driving methods .......................................................................................................................... 153 Frame frequency................................................................................................................................. 154 Driving method for LCD driver ............................................................................................................ 155 When using the booster circuit (LCDCR 15.2.1 15.2.2 15.2.3 15.3 15.2.3.1 15.2.3.2 LCD Display Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 Display data setting ............................................................................................................................ 157 Blanking .............................................................................................................................................. 158 15.3.1 15.3.2 iv 15.4 Control Method of LCD Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Initial setting ........................................................................................................................................ 159 Store of display data ........................................................................................................................... 159 Example of LCD drive output .............................................................................................................. 162 15.4.1 15.4.2 15.4.3 16. Input/Output Circuitry 16.1 16.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168 17. Electrical Characteristics 17.1 17.2 17.3 17.4 17.5 17.6 17.7 17.8 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Counter 1 input (ECIN) Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169 170 171 172 173 174 174 174 18. Package Dimension This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). v vi TMP86CH21AUG CMOS 8-Bit Microcontroller TMP86CH21AUG Product No. TMP86CH21AUG ROM (MaskROM) 16384 bytes RAM 512 bytes Package P-LQFP64-1010-0.50D OTP MCU TMP86PM29BUG Emulation Chip TMP86C929XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 19interrupt sources (External : 5 Internal : 14) 3. Input / Output ports (39 pins) Large current output: 4pins (Typ. 20mA), LED direct drive 4. Prescaler - Time base timer - Divider output function 5. Watchdog Timer 6. 18-bit Timer/Counter : 1ch - Timer Mode - Event Counter Mode - Pulse Width Measurement Mode - Frequency Measurement Mode 7. 8-bit timer counter : 4 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, 060116EBP * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86CH21AUG Programmable pulse generation (PPG) modes 8. 8-bit UART/SIO: 1 ch 9. 8-bit successive approximation type AD converter (with sample hold) Analog inputs: 8ch 10. Key-on wakeup : 4 ch 11. LCD driver/controller Built-in voltage booster for LCD driver With display memory LCD direct drive capability (MAX 32 seg x 4 com) 1/4,1/3,1/2duties or static drive are programmably selectable 12. Clock operation Single clock mode Dual clock mode 13. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 4.5 V to 5.5 V at 16MHz /32.768 kHz 2.7 V to 5.5 V at 8 MHz /32.768 kHz 1.8 V to 5.5 V at 4.2MHz /32.768 kHz Release by Page 2 TMP86CH21AUG 1.2 Pin Assignment VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET Figure 1-1 Pin Assignment Page 3 (STOP/INT5) P20 (AIN0) P60 (ECIN/AIN1) P61 (ECNT/AIN2) P62 (INT0/AIN3) P63 (STOP2/AIN4) P64 (STOP3/AIN5) P65 (STOP4/AIN6) P66 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 V2 V1 C1 C0 (DVO) P30 (TC3/PDO3/PWM3) P31 (TC4/PDO4/PWM4/PPG4) P32 (TC6/PDO6/PWM6/PPG6) P33 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 SEG3 SEG4 SEG5 SEG6 SEG7 P77 (SEG8) P76 (SEG9) P75 (SEG10) P74 (SEG11) P73 (SEG12) P72 (SEG13) P71 (SEG14) P70 (SEG15) P57 (SEG16) P56 (SEG17) P55 (SEG18) 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 P54(SEG19) P53(SEG20) P52(SEG21) P51(SEG22) P50(SEG23) P17(SEG24/SCK) P16(SEG25/TXD/SO) P15(SEG26/RXD/SI) P14(SEG27/INT3) P13(SEG28/INT2) P12(SEG29/INT1) P11(SEG30) P10(SEG31) AVDD VAREF P67(AIN7/STOP5) 1.3 Block Diagram TMP86CH21AUG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86CH21AUG 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/3) Pin Name P17 SEG24 SCK Pin Number Input/Output IO O IO IO O O O IO O I I IO O I IO O I IO O I IO O IO O IO O PORT17 LCD segment output 24 Serial Clock I/O PORT16 LCD segment output 25 UART data output Serial Data Output PORT15 LCD segment output 26 UART data input Serial Data Input PORT14 LCD segment output 27 External interrupt 3 input PORT13 LCD segment output 28 External interrupt 2 input PORT12 LCD segment output 29 External interrupt 1 input PORT11 LCD segment output 30 PORT10 LCD segment output 31 Functions 27 P16 SEG25 TXD SO P15 SEG26 RXD SI P14 SEG27 INT3 P13 SEG28 INT2 P12 SEG29 INT1 P11 SEG30 P10 SEG31 P22 XTOUT 26 25 24 23 22 21 20 7 PORT22 Resonator connecting pins(32.768kHz) for inputting external clock PORT21 Resonator connecting pins(32.768kHz) for inputting external clock PORT20 External interrupt 5 input STOP mode release signal input PORT33 PDO6/PWM6/PPG6 output TC6 input PORT32 PDO4/PWM4/PPG4 output TC4 input PORT31 PDO3/PWM3 output TC3 input PORT30 Divider Output PORT57 LCD segment output 16 PORT56 LCD segment output 17 P21 XTIN P20 INT5 STOP 6 IO I IO I I IO O I IO O I IO O I IO O IO O IO O 9 P33 PDO6/PWM6/PPG6 64 TC6 P32 PDO4/PWM4/PPG4 63 TC4 P31 PDO3/PWM3 62 TC3 P30 DVO 61 P57 SEG16 P56 SEG17 35 34 Page 5 1.4 Pin Names and Functions TMP86CH21AUG Table 1-1 Pin Names and Functions(2/3) Pin Name P55 SEG18 P54 SEG19 P53 SEG20 P52 SEG21 P51 SEG22 P50 SEG23 P67 AIN7 STOP5 P66 AIN6 STOP4 P65 AIN5 STOP3 P64 AIN4 STOP2 P63 AIN3 INT0 Pin Number 33 Input/Output IO O IO O IO O IO O IO O IO O IO I I IO I I IO I I IO I I IO I I IO I I IO I I IO I IO O IO O IO O IO O IO O IO O IO O PORT55 LCD segment output 18 PORT54 LCD segment output 19 PORT53 LCD segment output 20 PORT52 LCD segment output 21 PORT51 LCD segment output 22 PORT50 LCD segment output 23 Functions 32 31 30 29 28 17 PORT67 AD converter analog input 7 STOP5 input PORT66 AD converter analog input 6 STOP4 input PORT65 AD converter analog input 5 STOP3 input PORT64 AD converter analog input 4 STOP2 input PORT63 AD converter analog input 3 External interrupt 0 input PORT62 AD converter analog input 2 ECNT input PORT61 AD converter analog input 1 ECIN input PORT60 AD converter analog input 0 PORT77 LCD segment output 8 PORT76 LCD segment output 9 PORT75 LCD segment output 10 PORT74 LCD segment output 11 PORT73 LCD segment output 12 PORT72 LCD segment output 13 PORT71 LCD segment output 14 16 15 14 13 P62 AIN2 ECNT P61 AIN1 ECIN P60 AIN0 P77 SEG8 P76 SEG9 P75 SEG10 P74 SEG11 P73 SEG12 P72 SEG13 P71 SEG14 12 11 10 43 42 41 40 39 38 37 Page 6 TMP86CH21AUG Table 1-1 Pin Names and Functions(3/3) Pin Name P70 SEG15 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 SEG0 COM3 COM2 COM1 COM0 V3 V2 V1 C1 C0 XIN XOUT RESET Pin Number 36 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 2 3 8 4 18 19 5 1 Input/Output IO O O O O O O O O O O O O O I I I I I I O IO I I I I I PORT70 LCD segment output 15 LCD segment output 7 LCD segment output 6 LCD segment output 5 LCD segment output 4 LCD segment output 3 LCD segment output 2 LCD segment output 1 LCD segment output 0 LCD common output 3 LCD common output 2 LCD common output 1 LCD common output 0 LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin LCD voltage booster pin Functions Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal input/output Test pin for out-going test. Normally, be fixed to low. Analog reference voltage input (High) AD circuit power supply +5V 0(GND) TEST VAREF AVDD VDD VSS Page 7 1.4 Pin Names and Functions TMP86CH21AUG Page 8 TMP86CH21AUG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86CH21AUG memory is composed MaskROM, RAM, DBR(Data buffer register) and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86CH21AUG memory address map. 0000H SFR 003FH 0040H 64 bytes SFR: RAM 023FH 0F80H 512 bytes RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack DBR: DBR 0FFFH C000H 128 bytes Data buffer register includes: Peripheral control registers Peripheral status registers LCD display memory MaskROM: Program memory MaskROM FFC0H FFDFH FFE0H FFFFH 16384 bytes Vector table for vector call instructions (32 bytes) Vector table for interrupts (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (MaskROM) The TMP86CH21AUG has a 16384 bytes (Address C000H to FFFFH) of program memory (MaskROM ). 2.1.3 Data Memory (RAM) The TMP86CH21AUG has 512bytes (Address 0040H to 023FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. Page 9 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example :Clears RAM to "00H". (TMP86CH21AUG) LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC, 01FFH (HL), A HL BC F, SRAMCLR ; Start address setup ; Initial value (00H) setup 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register Clock generator XIN fc TBTCR 0036H High-frequency clock oscillator XOUT XTIN Timing generator fs Standby controller 0038H SYSCR1 0039H SYSCR2 Low-frequency clock oscillator XTOUT System clocks Clock generator control System control registers Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 10 TMP86CH21AUG High-frequency clock XIN XOUT XIN XOUT (Open) XTIN Low-frequency clock XTOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 11 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 7. LCD 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 fc or fs Main system clock generator SYSCK DV7CK Machine cycle counters High-frequency clock fc Low-frequency clock fs 12 fc/4 S A 123456 B Y Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S B0 B1 A0 Y0 A1 Y1 Multiplexer Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 12 TMP86CH21AUG Timing Generator Control Register TBTCR (0036H) 7 (DVOEN) 6 (DVOCK) 5 4 DV7CK 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86CH21AUG is placed in this mode after reset. Page 13 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 Page 14 TMP86CH21AUG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 15 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG IDLE0 mode Reset release RESET IDLE1 mode (a) Single-clock mode Note 2 SYSCR2 IDLE2 mode Interrupt NORMAL2 mode SYSCR2 SLEEP1 mode (b) Dual-clock mode SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode High Frequency Low Frequency CPU Core TBT Other Peripherals Reset Operate 4/fc [s] Machine Cycle Time RESET NORMAL1 Single clock IDLE1 IDLE0 STOP NORMAL2 IDLE2 SLOW2 Dual clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Oscillation Stop Oscillation Reset Operate Stop Halt Reset Operate Halt Operate with high frequency Halt - 4/fc [s] Oscillation Halt Operate with low frequency Halt Operate with low frequency Operate Operate 4/fs [s] Halt Halt Halt - Page 16 TMP86CH21AUG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP RELM RETM OUTEN STOP mode start Release method for STOP mode Operating mode after STOP mode Port output during STOP mode 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) 0: Edge-sensitive release 1: Level-sensitive release 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output kept Return to NORMAL mode Return to SLOW mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W R/W R/W R/W WUT Warm-up time at releasing STOP mode 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 214/fc R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: When the key-on wakeup is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHALT 1 0 (Initial value: 1000 *0**) XEN XTEN High-frequency oscillator control Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) TG control (IDLE0 and SLEEP0 modes) 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W R/W SYSCK IDLE TGHALT Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator, *; Don't care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Page 17 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG 2.2.4 Operating Mode Control STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP5 to STOP2) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 2.2.4.1 Note 1: The STOP mode can be released by either the STOP or key-on wakeup pin (STOP5 to STOP2). However, because the STOP pin is different from the key-on wakeup and can not inhibit the release input, the STOP pin must be used for releasing STOP mode. Note 2: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high or setting the STOP5 to STOP2 pin input which is enabled by STOPCR. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high or STOP5 to STOP2 input is low, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low or STOP5 to STOP2 input is high. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS DI SET (SYSCR1). 7 (SYSCR1), 01010000B (P2PRD). 0 F, SSTOPH ; IMF 0 ; Starts STOP mode ; Sets up the level-sensitive release mode ; Wait until the STOP pin input goes low level Page 18 TMP86CH21AUG Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1). 7 (P2PRD). 0 F, SINT5 (SYSCR1), 01010000B ; To reject noise, STOP mode does not start if port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 ; Starts STOP mode STOP pin XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. VIH Warm up NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOP5 to STOP2 pin input for releasing STOP mode in edge-sensitive release mode. Example :Starting STOP mode from NORMAL mode DI LD (SYSCR1), 10010000B ; IMF 0 ; Starts after specified to the edge-sensitive release mode STOP pin XOUT pin NORMAL operation STOP mode started by the program. STOP operation VIH Warm up NORMAL operation STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode Page 19 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024 Return to SLOW Mode 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 20 Turn off Oscillator circuit Turn on Main system clock a+3 SET (SYSCR1). 7 n+1 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+2 n+3 n+4 Halt Program counter a+2 Instruction execution Divider n 0 Figure 2-9 STOP Mode Start/Release a+4 Instruction address a + 2 Page 21 0 1 (b) STOP mode release Warm up STOP pin input Oscillator circuit Turn off Turn on Main system clock a+5 Instruction address a + 3 Program counter a+3 a+6 Instruction address a + 4 Instruction execution Halt Divider 0 Count up 2 3 TMP86CH21AUG 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input No No Interrupt request Yes "0" IMF Reset Normal release mode "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 22 TMP86CH21AUG * Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 23 Main system clock 2.2 System Clock Controller 2. Operational Description Interrupt request a+2 SET (SYSCR2). 4 Operate Halt a+3 Program counter Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Main system clock Interrupt request a+3 Instruction address a + 2 Operate Normal release mode a+4 Program counter Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 24 a+3 Acceptance of interrupt Operate Operate Interrupt release mode Instruction execution Halt Watchdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt Watchdog timer Halt TMP86CH21AUG (b) IDLE1/2 and SLEEP1/2 modes release TMP86CH21AUG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input No No TBT source clock falling edge Yes TBTCR Yes Reset No No (Normal release mode) Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 25 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG * Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR (1) Normal release mode (IMF*EF6*TBTCR (2) Interrupt release mode (IMF*EF6*TBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR Page 26 Main system clock Interrupt request a+2 a+3 Program counter Instruction execution SET (SYSCR2). 2 Halt Watchdog timer Operate (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Main system clock TBT clock a+3 a+4 Program counter Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 27 Instruction address a + 2 Operate Normal release mode a+3 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt Acceptance of interrupt Operate Interrupt release mode (b) IDLE and SLEEP0 modes release TMP86CH21AUG Watchdog timer Halt 2. Operational Description 2.2 System Clock Controller TMP86CH21AUG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET LD LD LDW DI SET EI SET : PINTTC4: CLR SET (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 28 TMP86CH21AUG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET LD LD LD DI SET EI SET : PINTTC4: CLR CLR (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 29 2.2 System Clock Controller 2. Operational Description Highfrequency clock Lowfrequency clock Main system clock Turn off SYSCK XEN CLR (SYSCR2). 7 SLOW2 mode (a) Switching to the SLOW mode Instruction execution SET (SYSCR2). 5 NORMAL2 mode SLOW1 mode Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 30 CLR (SYSCR2). 5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2). 7 TMP86CH21AUG SLOW1 mode NORMAL2 mode TMP86CH21AUG 2.3 Reset Circuit The TMP86CH21AUG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s] (The RESET pin outputs "L" level). The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 MHz) when power is turned on. RESET pin outputs "L" level during maximum 24/fc[s] (1.5s at 16.0MHz). Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) (PC) (SP) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latches of I/O ports Not initialized Not initialized 0 0 Control registers 0 LCD data buffer RAM Refer to each of control register Not initialized Not initialized Refer to I/O port circuitry Watchdog timer Enable Prescaler and divider of timing generator 0 On-chip Hardware Initial Value 2.3.1 External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 31 2. Operational Description 2.3 Reset Circuit TMP86CH21AUG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution JP a Address trap is occurred ("L" output) Maximum 24/fc [s] Note 3 4/fc to 12/fc [s] Reset release Instruction at address r RESET output 16/fc [s] Internal reset signal Note 1: Address "a" is in the SFR, DBR or on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 System clock reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 Page 32 TMP86CH21AUG Page 33 2. Operational Description 2.3 Reset Circuit TMP86CH21AUG Page 34 TMP86CH21AUG 3. Interrupt Control Circuit The TMP86CH21AUG has a total of 19 interrupt sources excluding reset, of which 3 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE FFEC Interrupt Factors Internal/External Internal Internal Internal Internal External External Internal External Internal Internal Internal Internal Internal Internal Internal External Internal External Internal (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INT0 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF4 = 1, INT0EN = 1 IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1 IMF* EF9 = 1, IL9ER = 0 IMF* EF9 = 1, IL9ER = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1 IMF* EF13 = 1 IMF* EF14 = 1, IL14ER = 0 IMF* EF14 = 1, IL14ER = 1 IMF* EF15 = 1, IL15ER = 0 IMF* EF15 = 1, IL15ER = 1 Priority 1 2 2 2 2 5 6 7 8 9 10 INT1 INTTBT INT2 INTTC1 INTRXD INTSIO INTTXD INTTC4 INTTC6 INTADC INT3 INTTC3 INT5 IL10 IL11 IL12 IL13 IL14 FFEA FFE8 FFE6 FFE4 FFE2 11 12 13 14 15 IL15 FFE0 16 INTTC5 Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL)). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 3.1 Interrupt latches (IL15 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Page 35 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CH21AUG Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". 3.2.2 Individual interrupt enable flags (EF15 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute nor- Page 36 TMP86CH21AUG mally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 37 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86CH21AUG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) IL15 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000***0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 EF14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) EF15 to EF4 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 38 TMP86CH21AUG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated. The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL. 1. INTRXD and INTSIO share the interrupt source level whose priority is 10. 2. INT3 and INTTC3 share the interrupt source level whose priority is 15. 3. INT5 and INTTC5 share the interrupt source level whose priority is 16. Interrupt source selector INTSEL (003EH) 7 6 IL9ER 5 4 3 2 1 IL14ER 0 IL15ER (Initial value: *0** **00) IL9ER IL14ER IL15ER Selects INTRXD or INTSIO Selects INT3 or INTTC3 Selects INT5 or INTTC5 0: INTRXD 1: INTSIO 0: INT3 1: INTTC3 0: INT5 1: INTTC5 R/W R/W R/W 3.4 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Page 39 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86CH21AUG 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFF2H FFF3H 03H D2H Vector D203H D204H 0FH 06H Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. Page 40 TMP86CH21AUG 3.4.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP A SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction SP b-5 b-4 b-3 b-2 b-1 b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.4.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Page 41 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86CH21AUG Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Page 42 TMP86CH21AUG Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.5 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.5.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM, DBR or SFR areas. 3.5.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.6 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.7 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). 3.8 External Interrupts The TMP86CH21AUG has 5 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT3. The INT0/P63 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P63 pin function selection are performed by the external interrupt control register (EINTCR). Page 43 3. Interrupt Control Circuit 3.8 External Interrupts TMP86CH21AUG Source Pin Enable Conditions Release Edge Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 IMF EF4 INT0EN=1 Falling edge INT1 INT1 IMF EF5 = 1 Falling edge or Rising edge INT2 INT2 IMF EF7 = 1 Falling edge or Rising edge INT3 INT3 IMF and EF14 = 1 IL14ER=0 Falling edge or Rising edge INT5 INT5 IMF EF15 = 1 and IL15ER=0 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 44 TMP86CH21AUG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 00** 000*) INT1NC INT0EN INT3 ES INT2 ES INT1 ES Noise reject time select P63/INT0 pin configuration INT3 edge select INT2 edge select INT1 edge select 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P63 input/output port 1: INT0 pin (Port P63 should be set to an input mode) 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge R/W R/W R/W R/W R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Page 45 3. Interrupt Control Circuit 3.8 External Interrupts TMP86CH21AUG Page 46 TMP86CH21AUG 4. Special Function Register (SFR) The TMP86CH21AUG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR) or the data buffer register (DBR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 0F80H to 0FFFH. This chapter shows the arrangement of the special function register (SFR) and data buffer register (DBR) for TMP86CH21AUG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H UARTSR ADCDR1 ADCDR2 Reserved Reserved Reserved UARTCR1 TC1SR Reserved TC3CR TC4CR TC5CR TC6CR TTREG3 TTREG4 TTREG5 TTREG6 P7PRD ADCCR1 ADCCR2 TREG1AL TREG1AM TREG1AH TREG1B TC1CR1 TC1CR2 P1PRD P2PRD P3PRD P5PRD P6CR Read Reserved P1DR P2DR P3DR P3OUTCR P5DR P6DR P7DR Write Page 47 4. Special Function Register (SFR) 4.1 SFR TMP86CH21AUG Address 0026H 0027H 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read Reserved LCDCR P1LCR P5LCR P7LCR PWREG3 PWREG4 PWREG5 PWREG6 Reserved Reserved Reserved Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH INTSEL PSW Write UARTCR2 WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 48 TMP86CH21AUG 4.2 DBR Address 0F80H 0F81H 0F82H 0F83H 0F84H 0F85H 0F86H 0F87H 0F88H 0F89H 0F8AH 0F8BH 0F8CH 0F8DH 0F8EH 0F8FH 0F90H 0F91H 0F92H 0F93H 0F94H 0F95H 0F96H 0F97H 0F98H 0F99H 0F9AH 0F9BH 0F9CH 0F9DH 0F9EH 0F9FH SIOSR RDBUF Reserved Reserved Reserved Reserved Read SEG1/0 SEG3/2 SEG5/4 SEG7/6 SEG9/8 SEG11/10 SEG13/12 SEG15/14 SEG17/16 SEG19/18 SEG21/20 SEG23/22 SEG25/24 SEG27/26 SEG29/28 SEG31/30 SIOBR0 SIOBR1 SIOBR2 SIOBR3 SIOBR4 SIOBR5 SIOBR6 SIOBR7 SIOCR1 SIOCR2 STOPCR TDBUF Write Address 0FA0H :: 0FBFH Read Reserved :: Reserved Write Address 0FC0H :: 0FDFH Read Reserved :: Reserved Write Address 0FE0H :: 0FFFH Read Reserved :: Reserved Write Note 1: Do not access reserved areas by the program. Page 49 4. Special Function Register (SFR) 4.2 DBR TMP86CH21AUG Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 50 TMP86CH21AUG 5. I/O Ports The TMP86CH21AUG has 6 parallel input/output ports (39 pins) as follows. Primary Function Port P1 Port P2 Port P3 Port P5 Port P6 Port P7 8-bit I/O port 3-bit I/O port 4-bit I/O port 8-bit I/O port 8-bit I/O port 8-bit I/O port Secondary Functions External interrupt input, serial interface input/output, UART input/output and segment output. Low-frequency resonator connections, external interrupt input, STOP mode release signal input. Timer/counter input/output and divider output. Segment output. Analog input, external interrupt input, timer/counter input and STOP mode release signal input. Segment output. Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several timer before processing. Figure 5-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle Fetch cycle Read cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD A, (x) Input strobe Data input (a) Input timing Fetch cycle Fetch cycle Write cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD (x), A Output strobe Data output Old (b) Output timing New Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 5-1 Input/Output Timing (Example) Page 51 5. I/O Ports 5.1 Port P1 (P17 to P10) TMP86CH21AUG 5.1 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output, UART input/output and segment output of LCD. When used as a segment pins of LCD, the respective bit of P1LCR should be set to "1". When used as an input port or a secondary function (except for segment) pins, the respective output latch (P1DR) should be set to "1" and its corresponding P1LCR bit should be set to "0". When used as an output port, the respective P1LCR bit should be set to "0". During reset, the output latch is initialized to "1". P1 port output latch (P1DR) and P1 port terminal input (P1PRD) are located on their respective address. When read the output latch data, the P1DR should be read and when read the terminal input data, the P1PRD register should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is read. Control input Terminal input (P1PRD) P1LCRi P1LCRi input Output latch data (P1DR) Data output (P1DR) Control output STOP OUTEN LCD data output D Q P1i Note: i = 7 to 0 D Q Output latch Figure 5-2 Port 1 7 P1DR (0001H) R/W P17 SEG24 SCK 6 P16 SEG25 SO TxD 6 5 P15 SEG26 SI RxD 5 4 P14 SEG27 INT3 4 3 P13 SEG28 INT2 3 2 P12 SEG29 INT1 2 1 P11 SEG30 0 P10 SEG31 (Initial value: 1111 1111) P1LCR (0029H) 7 1 0 (Initial value: 0000 0000) P1LCR Port P1/segment output control (set for each bit individually) 0: P1 input/output port or secondary function (expect for segment) 1: Segment output R/W P1PRD (0008H) Read only 7 P17 6 P16 5 P15 4 P14 3 P13 2 P12 1 P11 0 P10 Page 52 TMP86CH21AUG 5.2 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set to "1". During reset, the P2DR is initialized to "1". A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dualclock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports. It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address. When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD register should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable. Data input (P20PRD) Data input (P20) Data output (P20) Control input Data input (P21PRD) Osc. enable Data input (P21) Data output (P21) Data input (P22PRD) Data input (P22) Data output (P22) D Q P22 (XTOUT) D Q P21 (XTIN) D Q P20 (INT5, STOP) Output latch Output latch Output latch STOP OUTEN XTEN fs Figure 5-3 Port 2 P2DR (0002H) R/W P2PRD (0009H) Read only 7 6 5 4 3 2 P22 XTOUT 1 P21 XTIN 1 P21 0 P20 INT5 STOP (Initial value: **** *111) 7 6 5 4 3 2 P22 0 P20 Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Page 53 5. I/O Ports 5.3 Port P3 (P33 to P30) TMP86CH21AUG 5.3 Port P3 (P33 to P30) Port P3 is a 4-bit input/output port. It is also used as a timer/counter input/output, divider output. When used as a timer/counter output or divider output, respective output latch (P3DR) should be set to "1". It can be selected whether output circuit of P3 port is C-MOS output or a sink open drain individually, by setting P3OUTCR. When a corresponding bit of P3OUTCR is "0", the output circuit is selected to a sink open drain and when a corresponding bit of P3OUTCR is "1", the output circuit is selected to a C-MOS output. When used as an input port or timer/counter input, respective output control (P3OUTCR) should be set to "0" after P3DR is set to "1". During reset, the P3DR is initialized to "1", and the P3OUTCR is initialized to "0". P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address. When read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD register should be read. If a read instruction is executed for port P3, read data of bits 7 to 4 are unstable. STOP OUTEN P3OUTCRi P3OUTCRi input Data input (P3PRD) Data input (P3DR) Data output (P3DR) Control output Control input D Q D Q P3i Note: i = 3 to 0 Figure 5-4 Port 3 7 P3DR (0003H) R/W 6 5 4 3 P33 PWM6 PDO6 PPG6 2 P32 PWM4 PDO4 PPG4 1 P31 PWM3 PDO3 0 P30 DVO (Initial value: **** 1111) TC3 1 0 (Initial value: **** 0000) TC6 P3OUTCR (0004H) 7 6 5 4 3 TC4 2 P3OUTCR Port P3 output circuit control (set for each bit individually) 0: Sink open-drain output 1: C-MOS output R/W P3PRD (000AH) Read only 7 6 5 4 3 P33 2 P32 1 P31 0 P30 Page 54 TMP86CH21AUG 5.4 Port P5 (P57 to P50) Port P5 is an 8-bit input/output port which is also used as a segment pins of LCD. When used as input port, the respective output latch (P5DR) should be set to "1". During reset, the P5DR is initialized to "1". When used as a segment pins of LCD, the respective bit of P5LCR should be set to "1". When used as an output port, the respective P5LCR bit should be set to "0". P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address. When read the output latch data, the P5DR should be read and when read the terminal input data, the P5PRD register should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is read. STOP OUTEN P5LCRi P5LCRi input Data input (P5PRD) Data input (P5DR) Data output (P5DR) LCD data output D Q P5i Note: i = 7 to 0 D Q Output latch Figure 5-5 Port 5 P5DR (0005H) R/W P5LCR (002AH) 7 P57 SEG16 7 6 P56 SEG17 6 5 P55 SEG18 5 4 P54 SEG19 4 3 P53 SEG20 3 2 P52 SEG21 2 1 P51 SEG22 1 0 P50 SEG23 0 (Initial value: 0000 0000) (Initial value: 1111 1111) P5LCR Port P5/segment output control (set for each bit individually) 0: P5 input/output port 1: LCD segment output R/W P5PRD (000BH) Read only 7 P57 6 P56 5 P55 4 P54 3 P53 2 P52 1 P51 0 P50 Page 55 5. I/O Ports 5.5 Port P6 (P67 to P60) TMP86CH21AUG 5.5 Port P6 (P67 to P60) Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also used as an analog input, Key on Wake up input, timer/counter input and external interrupt input. Input/output modes is specified by the P6 control register (P6CR), the P6 output latch (P6DR), and ADCCR1 STOPj Key on Wake up Analog input AINDS SAIN P6CRi P6CRi input Data input (P6DR) D Q Data output (P6DR) Control input STOP D Q P6i Note 1: Note 2: Note 3: Note 4: i = 7 to 0, j = 7 to 4 STOP is bit7 in SYSCR1 SAIN is bit 0 to 3 in ADCCR1 STOPj is input select signal in a key on wake up. Figure 5-6 Port 6 Page 56 TMP86CH21AUG P6DR (0006H) R/W 7 P67 AIN7 STOP5 7 6 P66 AIN6 STOP4 6 5 P65 AIN5 STOP3 5 4 P64 AIN4 STOP2 4 3 P63 AIN3 INT0 2 P62 AIN2 ECNT 2 1 P61 AIN1 ECIN 1 0 P60 AIN0 0 (Initial value: 0000 0000) (Initial value: 0000 0000) 3 P6CR (000CH) AINDS = 1 (AD unused) P6CR I/O control for port P6 (specified for each bit) P6DR = "0" 0 1 Input "0" fixed P6DR = "1" Input mode AINDS = 0 (AD used) P6DR = "0" AD input P6DR = "1" Input mode R/W Output mode Output mode Note 1: Do not set output mode to pin which is used for an analog input. Note 2: When used as an INT0, ECNT and ECIN pins of a secondary function, the respective bit of P6CR should be set to "0" and the P6 should set to "1". Note 3: When used as an STOP2 to STOP5 pins of Key on Wake up, the respective bit of P6CR should be set to "0". Note 4: When a read instruction for port P6 is executed, the bit of Analog input mode becomes read data "0". Note: Although P6DR is a read/writer register, because it is also used as an input mode control function, read-modifywrite instructions such as bit manipulate instructions cannot be used. Read-modify-write instruction writes the all data of 8-bit after data is read and modified. Because a bit setting Input mode read data of terminal, the output latch is changed by these instruction. So P6 port can not input data. Page 57 5. I/O Ports 5.6 Port P7 (P77 to P70) TMP86CH21AUG 5.6 Port P7 (P77 to P70) Port P7 is an 8-bit input/output port which is also used as a segment pins of LCD. When used as input port, the respective output latch (P7DR) should be set to "1". During reset, the P7DR is initialized to "1". When used as a segment pins of LCD, the respective bit of P7LCR should be set to "1" and its corresponding P7LCR bit should be set to "0". When used as an output port, the respective P7LCR bit should be set to "0". P7 port output latch (P7DR) and P7 port terminal input (P7PRD) are located on their respective address. When read the output latch data, the P7DR should be read and when read the terminal input data, the P7PRD register should be read. If the terminal input data which is configured as LCD segment output is read, unstable data is read. STOP OUTEN P7LCRi P7LCRi input P7LCRi Data input (P7PRD) Data input (P7DR) Data output (P7DR) LCD data output D Q P7i Note: i = 7 to 0 D Q Output latch Figure 5-7 Port 7 P7DR (0007H) R/W P7LCR (002BH) 7 P77 SEG8 7 6 P76 SEG9 6 5 P75 SEG10 5 4 P74 SEG11 4 3 P73 SEG12 3 2 P72 SEG13 2 1 P71 SEG14 1 0 P70 SEG15 0 (Initial value: 0000 0000) (Initial value: 1111 1111) P7LCR Port P7/segment output control (set for each bit individually) 0: P7 input/Output port 1: Segment output R/W P7PRD (000DH) Read only 7 P77 6 P76 5 P75 4 P74 3 P73 2 P72 1 P71 0 P70 Page 58 TMP86CH21AUG 6. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 6.1 Time Base Timer 6.1.1 Configuration MPX fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 6-1 Time Base Timer configuration 6.1.2 Control Time Base Timer is controled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 fc/223 fc/221 fc/216 fc/2 14 DV7CK = 1 fs/215 fs/213 fs/28 fs/2 6 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - - - - - - R/W TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/213 fc/2 12 fs/25 fs/2 4 fc/211 fc/2 9 fs/23 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 59 6. Time Base Timer (TBT) 6.1 Time Base Timer TMP86CH21AUG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRL) . 6 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 6-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 6.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 6-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 6-2 Time Base Timer Interrupt Page 60 TMP86CH21AUG 6.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 6.2.1 Configuration Output latch Data output D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 6-3 Divider Output 6.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 fs/25 fs/24 fs/23 fs/22 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 61 6. Time Base Timer (TBT) 6.2 Divider Output (DVO) TMP86CH21AUG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 6-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k Page 62 TMP86CH21AUG 7. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 Watchdog Timer Configuration Reset release fc/2 or fs/2 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 23 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 7-1 Watchdog Timer Configuration Page 63 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86CH21AUG 7.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 7.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 64 TMP86CH21AUG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 217/fs 215/fs 213/fs 211/fs SLOW1/2 mode 217/fs 215fs 213fs 211/fs Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "1.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 7.2.2 Watchdog Timer Enable Setting WDTCR1 Page 65 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86CH21AUG 7.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary coutner : WDTEN 0, WDTCR2 Disable code Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m NORMAL1/2 mode DV7CK = 1 4 1 250 m 62.5 m SLOW mode 4 1 250 m 62.5 m 7.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 023FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 66 TMP86CH21AUG 7.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs (High-Z) Write 4EH to WDTCR2 WDT reset output Figure 7-2 Watchdog Timer Interrupt/Reset Page 67 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86CH21AUG 7.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area Select opertion at address trap 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is reguired) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 7.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 7.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 7.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 68 TMP86CH21AUG 7.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 69 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86CH21AUG Page 70 8.1 Configuration fc/212 or fs/24 TREG1B Y S 2 SGEDG 1 Window pulse generator TC1M 2 INTTC1 fc/213 or fs/25 fc/214 or fs/26 A B C PWM6/PDO6/PPG6 WGPSCK TC6OUT 1 Edge detector C B A Y S Pulse width measurement mode P33 Pin 8. 18-Bit Timer/Counter (TC1) ECNT Pin TC1S TC1CK TC1M TC1C TMP86CH21AUG TC1CR1 SEG SGP SGEDG WGPSCK TC6OUT Figure 8-1 Timer/Counter1 10 11 00 S CMP Y CLEAR signal 18- bit up-counter H Timer/Event count modes Frequency measurement mode Page 71 Y C D E F G B A 3 22 1 12121 TC1CR2 SEG 1 ECIN Pin Edge detector F/F 1 1 TC1SR TREG1AL TREG1AM TREG1AH fs/215 or fc/223 fs/25 or fc/213 fs/23 or fc/211 fc/27 fc/23 fs fc 8. 18-Bit Timer/Counter (TC1) 8.2 Control TMP86CH21AUG 8.2 Control The Timer/counter 1 is controlled by timer/counter 1 control registers (TC1CR1/TC1CR2), an 18-bit timer register (TREG1A), and an 8-bit internal window gate pulse setting register (TREG1B). Timer register 7 TREG1AH (0012H) R/W - 6 - 5 - 4 - 3 - 2 - 1 0 (Initial value: 00) TREG1AH 7 TREG1AM (0011H) R/W 6 5 4 3 2 1 0 (Initial value: 0000 0000) TREG1AM 7 TREG1AL (0010H) R/W 6 5 4 3 2 1 0 (Initial value: 0000 0000) TREG1AL 7 TREG1B (0013H) 6 Ta 5 4 3 2 Tb 1 0 (Initial value: 0000 0000) NORMAL1/2,IDLE1/2 modes WGPSCK DV7CK=0 Setting "H" level period of the window gate pulse 00 01 10 00 01 10 (16 - Ta) x 212/fc (16 - Ta) x 2 /fc (16 - Ta) x 214/fc 13 DV7CK=1 (16 - Ta) x 24/fs (16 - Ta) x 2 /fs (16 - Ta) x 26/fs 5 SLOW1/2, SLEEP1/2 modes (16 - Ta) x 24/fs (16 - Ta) x 25/fs (16 - Ta) x 26/fs (16 - Tb) x 24/fs (16 - Tb) x 25/fs (16 - Tb) x 26/fs R/W Ta Tb Setting "L" level period of the window gate pulse (16 - Tb) x 212/fc (16 - Tb) x 213/fc (16 - Tb) x 214/fc (16 - Tb) x 24/fs (16 - Tb) x 25/fs (16 - Tb) x 26/fs Page 72 TMP86CH21AUG Timer/counter 1 control register 1 7 TC1CR1 (0014H) TC1C 6 TC1S 5 4 3 TC1CK 2 1 TC1M 0 (Initial value: 1000 1000) TC1C Counter/overfow flag controll 0: 1: 00: 10: *1: Clear Counter/overflow flag ( "1" is automatically set after clearing.) Not clear Counter/overflow flag Stop and counter clear and overflow flag clear Start Reserved NORMAL1/2,IDLE1/2 modes DV7CK="0" DV7CK="1" fc fs fs/215 fs/25 fs/23 fc/27 fc/23 SLOW1/2 mode fc fs/215 fs/25 fs/23 SLEEP1/2 mode fc fs/215 fs/25 fs/23 - R/W TC1S TC1 start control R/W TC1CK TC1 source clock select 000: 001: 010: 011: 100: 101: 110: 111: 00: 01: 10: 11: fc fs fc/223 fc/2 13 R/W fc/211 fc/2 7 fc/23 External clock (ECIN pin input) Timer/Event counter mode Reserved Pulse width measurement mode Frequency measurement mode TC1M TC1 mode select R/W Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] * ; Don't care Note 2: Writing to the low-byte of the timer register 1A (TREG1AL, TREG1AM), the compare function is inhibited until the highbyte (TREG1AH) is written. Note 3: Set the mode and source clock, and edge (selection) when the TC1 stops (TC1S=00). Note 4: "fc" can be selected as the source clock only in the timer mode during SLOW mode and in the pulse width measurement mode during NORMAL 1/2 or IDLE 1/2 mode. Note 5: When a read instruction is executed to the timer register (TREG1A), the counter immediate value, not the register set value, is read out. Therefore it is impossible to read out the written value of TREG1A. To read the counter value, the read instruction should be executed when the counter stops to avoid reading unstable value. Note 6: Set the timer register (TREG1A) to 1. Note 7: When using the timer mode and pulse width measurement mode, set TC1CK (TC1 source clock select) to internal clock. Note 8: When using the event counter mode, set TC1CK (TC1 source clock select) to external clock. Note 9: Because the read value is different from the written value, do not use read-modify-write instructions to TREG1A. Note 10:fc/27, fc/23can not be used as source clock in SLOW/SLEEP mode. Note 11:The read data of bits 7 to 2 in TREG1AH are always "0". (Data "1" can not be written.) Page 73 8. 18-Bit Timer/Counter (TC1) 8.2 Control TMP86CH21AUG Timer/Counter 1 control register 2 7 TC1CR2 (0015H) SEG 6 SGP 5 4 SGEDG 3 WGPSCK 2 1 TC6OUT 0 "0" (Initial value: 0000 000*) SEG External input clock (ECIN) edge select 0: 1: 00: 01: 10: 11: 0: 1: Counts at the falling edge Counts at the both (falling/rising) edges ECNT input Internal window gate pulse (TREG1B) PWM6/PDO6/PPG6 (TC6)output Reserved Interrupts at the falling edge Interrupts at the falling/rising edges NORMAL1/2,IDLE1/2 modes DV7CK="0" DV7CK="1" 24/fs 2 /fs 26/fs Reserved 5 R/W SGP Window gate pulse select R/W SGEDG Window gate pulse interrupt edge select SLOW1/2 mode 24/fs 2 /fs 26/fs Reserved 5 SLEEP1/2 mode 24/fs 25/fs 26/fs Reserved R/W R/W WGPSCK Window gate pulse source clock select 00: 01: 10: 11: 0: 1: 212/fc 2 /fc 214/fc Reserved Output to P33 No output to P33 13 TC6OUT TC6 output (PWM6/PDO6/PPG6) external output select Note 1: fc; High-frequency clock [Hz] fs; Low-frequency clock [Hz] *; Don't care Note 2: Set the mode, source clock, and edge (selection) when the TC1 stops (TC1S = 00). Note 3: If there is no need to use PWM6/PDO6/PPG6 as window gate pulse of TC1 always write "0" to TC6OUT. Note 4: Make sure to write TC1CR2 "0" to bit 0 in TC1CR2. Note 5: When using the event counter mode or pulse width measurement mode, set SEG to "0". Page 74 TMP86CH21AUG TC1 status register 7 TC1SR (0016H) HECF 6 HEOVF 5 "0" 4 "0" 3 "0" 2 "0" 1 "0" 0 "0" (Initial value: 0000 0000) HECF Operating Status monitor 0: 1: 0: 1: Stop (during Tb) or disable Under counting (during Ta) No overflow Overflow status Read only HEOVF Counter overflow monitor 8.3 Function TC1 has four operating modes. The timer mode of the TC1 is used at warm-up when switching form SLOW mode to NORMAL2 mode. 8.3.1 Timer mode In this mode, counting up is performed using the internal clock. The contents of TREGIA are compared with the contents of up-counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. Counting up resumes after the counter is cleared. Table 8-1 Source clock (internal clock) of Timer/Counter 1 Source Clock NORMAL1/2, IDLE1/2 Mode SLOW Mode DV7CK = 0 fc/223 [Hz] fc/213 fc/211 fc/27 fc/23 fc fs DV7CK = 1 fs/215 [Hz] fs/25 fs/23 fc/27 fc/23 fc fs fs/215 [Hz] fs/25 fs/23 fc (Note) fs/215 [Hz] fs/25 fs/23 0.52 s 512 ms 128 ms 8 ms 0.5 ms 62.5 ns SLEEP Mode fc = 16 MHz Resolution fs =32.768 kHz 1s 0.98 ms 244 ms 30.5 ms Maximum Time Setting fc = 16 MHz 38.2 h 2.2 min 0.6 min 2.1 s 131.1 ms 16.4 ms fs =32.768 kHz 72.8 h 4.3 min 1.07 min 8s Note: When fc is selected for the source clock in SLOW mode, the lower bits 11 of TREG1A is invalid, and a match of the upper bits 7 makes interrupts. Page 75 8. 18-Bit Timer/Counter (TC1) 8.3 Function TMP86CH21AUG Command Start Internal clock Up counter 0 1 2 3 4 n-1 n0 1 2 3 4 5 6 TREG1A n Match detect Counter clear INTTC1 interrupt Figure 8-2 Timing chart for timer mode 8.3.2 Event Counter mode It is a mode to count up at the falling edge of the ECIN pin input. When using this mode, set TC1CR1 Start ECIN pin input Up counter 0 1 2 n-1 n 0 1 2 TREG1A n Match Detect Counter clear INTTC1 interrupt Figure 8-3 Event counter mode timing chart Page 76 TMP86CH21AUG 8.3.3 Pulse Width Measurement mode In this mode, pulse widths are counted on the falling edge of logical AND-ed pulse between ECIN pin input (window pulse) and the internal clock. When using this mode, set TC1CR1 Note:In pulse width measurement mode, if TC1CR1 Example : TC1STOP : | DI CLR LD LD SET EI | | (EIRH). 0 (TC1CR1), 00011010B (ILH), 11111110B (EIRH). 0 | ; Clear IMF ; Clear bit0 of EIRH ; Stop timer couter 1 ; Clear bit0 of ILH ; Set bit0 of EIRH ; Set IMF Note 1: When SGEDG (window gate pulse interrupt edge select) is set to both edges and ECIN pin input is "1" in the pulse width measurement mode, an INTTC1 interrupt is generated by setting TC1S (TC1 start control) to "10" (start). Note 2: In the pulse width measurement mode, HECF (operating status monitor) cannot used. Note 3: Because the up counter is counted on the falling edge of logical AND-ed pulse (between ECIN pin input and the internal clock), if ECIN input becomes falling edge while internal source clock is "H" level, the up counter stops plus "1". Count Start Count Stop Count Start ECIN pin input Internal clock AND-ed pulse (Internal signal) Up counter 0 1 2 3 n-2 n-1 n n+1 Read Clear Interrupt 0 1 2 INTTC1 interrupt TC1CR1 Figure 8-4 Pulse width measurement mode timing chart Page 77 8. 18-Bit Timer/Counter (TC1) 8.3 Function TMP86CH21AUG 8.3.4 Frequency Measurement mode In this mode, the frequency of ECIN pin input pulse is measured. When using this mode, set TC1CR1 When the internal window gate pulse is selected, the window gate pulse is set as follows. Table 8-2 Internal window gate pulse setting time NORMAL1/2,IDLE1/2 modes WGPSCK DV7CK=0 Setting "H" level period of the window gate pulse 00 01 10 00 01 10 (16 - Ta) x 212/fc (16 - Ta) x 213/fc 14 DV7CK=1 (16 - Ta) x 24/fs (16 - Ta) x 25/fs 6 SLOW1/2, SLEEP1/2 modes (16 - Ta) x 24/fs (16 - Ta) x 25/fs (16 - Ta) x 26/fs (16 - Tb) x 24/fs (16 - Tb) x 25/fs (16 - Tb) x 26/fs R/W Ta (16 - Ta) x 2 /fc (16 - Tb) x 212/fc (16 - Tb) x 2 /fc (16 - Tb) x 214/fc 13 (16 - Ta) x 2 /fs (16 - Tb) x 24/fs (16 - Tb) x 2 /fs (16 - Tb) x 26/fs 5 Tb Setting "L" level period of the window gate pulse The internal window gate pulse consists of "H" level period (Ta) that is counting time and "L" level period (Tb) that is counting stop time. Ta or Tb can be individually set by TREG1B. One cycle contains Ta + Tb. Note 1: Because the internal window gate pulse is generated in synchronization with the internal divider, it may be delayed for a maximum of one cycle of the source clock (WGPSCK) immediately after start of the timer. Note 2: Set the internal window gate pulse when the timer counter is not operating or during the Tb period. When Tb is overwritten during the Tb period, the update is valid from the next Tb period. Note 3: In case of TC1CR2 Page 78 TMP86CH21AUG Table 8-3 Table Setting Ta and Tb (WGPSCK = 10, fc = 16 MHz) Setting Value 0 1 2 3 4 5 6 7 Setting time 16.38ms 15.36ms 14.34ms 13.31ms 12.29ms 11.26ms 10.24ms 9.22ms Setting Value 8 9 A B C D E F Setting time 8.19ms 7.17ms 6.14ms 5.12ms 4.10ms 3.07ms 2.05ms 1.02ms Table 8-4 Table Setting Ta and Tb (WGPSCK = 10, fs = 32.768 kHz) Setting Valuen 0 1 2 3 4 5 6 7 Setting time 31.25ms 29.30ms 27.34ms 25.39ms 23.44ms 21.48ms 19.53ms 17.58ms Setting Value 8 9 A B C D E F Setting time 15.63ms 13.67ms 11.72ms 9.77ms 7.81ms 5.86ms 3.91ms 1.95ms Page 79 8. 18-Bit Timer/Counter (TC1) 8.3 Function TMP86CH21AUG ECIN pin input Window gate pulse AND-ed pulse (Internal signal) Up counter 0 1 2 3 4 5 6 0 1 2 3 4 5 6 Ta Tb Ta INTTC1 interrupt Read Clear TC1CR1 TC1CR2 ECIN pin input Window gate pulse Up counter 0 Ta Tb Ta 1 2 3 4 5 6 7 8 9 10 11 12 13 0 1 2 3 4 5 6 7 8 9 10 11 12 INTTC1 interrupt Read Clear TC1CR1 Figure 8-5 Timing chart for the frequency measurement mode (Window gate pulse falling interrupt) Page 80 TMP86CH21AUG 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC4 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TC4 pin TC4M TC4S TFF4 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC4S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F4 PDO4/PWM4/ PPG4 pin TC4CK TC4CR TTREG4 PWREG4 PWM, PPG mode DecodeEN TFF4 PDO, PWM, PPG mode 16-bit mode TC3S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TC3 pin TC3M TC3S TFF3 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC3 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F3 PDO3/PWM3/ pin TC3CK TC3CR TTREG3 PWREG3 PWM mode DecodeEN TFF3 PDO, PWM mode 16-bit mode Figure 9-1 8-Bit TimerCouter 3, 4 Page 81 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH21AUG 9.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (001CH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG3 (002CH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG3) setting while the timer is running. Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 3 Control Register TC3CR (0018H) 7 TFF3 6 5 TC3CK 4 3 TC3S 2 1 TC3M 0 (Initial value: 0000 0000) TFF3 Time F/F3 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC3CK Operating clock selection [Hz] 010 011 100 101 110 111 TC3S TC3 start control 0: 1: 000: 001: TC3M TC3M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC4M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running. Note 3: To stop the timer operation (TC3S= 1 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer operation (TC3S= 0 1), TC3M, TC3CK and TFF3 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR Page 82 TMP86CH21AUG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 93. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 83 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH21AUG The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (001DH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG4 (002DH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running. Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 4 Control Register TC4CR (0019H) 7 TFF4 6 5 TC4CK 4 3 TC4S 2 1 TC4M 0 (Initial value: 0000 0000) TFF4 Timer F/F4 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC4 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC4CK Operating clock selection [Hz] 010 011 100 101 110 111 TC4S TC4 start control 0: 1: 000: 001: 010: TC4M TC4M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running. Note 3: To stop the timer operation (TC4S= 1 0), do not change the TC4M, TC4CK and TFF4 settings. To start the timer operation (TC4S= 0 1), TC4M, TC4CK and TFF4 can be programmed. Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC4 overflow signal regardless of the TC3CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR Page 84 TMP86CH21AUG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR Table 9-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note 2: : Available source clock Table 9-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note2: : Available source clock Page 85 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH21AUG Table 9-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG4, 3) 65535 256 (TTREG4, 3) 65535 2 (PWREG4, 3) 65534 1 (PWREG4, 3) < (TTREG4, 3) 65535 16-bit PPG and (PWREG4, 3) + 1 < (TTREG4, 3) Register Value Note: n = 3 to 4 Page 86 TMP86CH21AUG 9.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 9.3.1 8-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 9-4 Source Clock for TimerCounter 3, 4 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Repeated Cycle fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter4, fc = 16.0 MHz) LD DI SET EI LD LD (TC4CR), 00010000B (TC4CR), 00011000B : Sets the operating cock to fc/27, and 8-bit timer mode. : Starts TC4. (EIRH). 3 : Enables INTTC4 interrupt. (TTREG4), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 87 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH21AUG TC4CR Internal Source Clock Counter TTREG4 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-2 8-Bit Timer Mode Timing Chart (TC4) 9.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC4CR Counter TTREG4 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-3 8-Bit Event Counter Mode Timing Chart (TC4) 9.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 88 TMP86CH21AUG Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD LD LD (TTREG4), 3DH (TC4CR), 00010001B (TC4CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC4. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 89 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Counter 0 1 2 Figure 9-4 8-Bit PDO Mode Timing Chart (TC4) Match detect Match detect Match detect Page 90 TTREG4 ? n Match detect Timer F/F4 Set F/F PDO4 pin INTTC4 interrupt request Held at the level when the timer is stopped TMP86CH21AUG TMP86CH21AUG 9.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 9-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 91 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock n Write to PWREG4 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG4 Figure 9-5 8-Bit PWM Mode Timing Chart (TC4) m Shift Shift m Match detect Match detect Page 92 n One cycle period m PWREG4 ? n p Shift p Match detect Shift Shift registar ? n Match detect Timer F/F4 PWM4 pin n p INTTC4 interrupt request TMP86CH21AUG TMP86CH21AUG 9.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the timer mode, fix TCjCR Table 9-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC3CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRH). 3 : Enables INTTC4 interrupt. (TTREG3), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC4CR), 04H (TC4CR), 0CH TC4CR Internal source clock Counter TTREG3 (Lower byte) TTREG4 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 9-6 16-Bit Timer Mode Timing Chart (TC3 and TC4) Page 93 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH21AUG 9.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the event counter mode, fix TCjCR 9.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 94 TMP86CH21AUG CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the PWM4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4 pin during the warm-up period time after exiting the STOP mode. Table 9-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2 s fs = 32.768 kHz 16 s - - - 2s - - 8.2 ms 4.1 ms Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG3), 07D0H (TC3CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC4CR), 056H (TC4CR), 05EH Page 95 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock an Write to PWREG3 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG3 FFFF 0 1 cp PWREG3 (Lower byte) ? Write to PWREG4 n m p Write to PWREG4 Figure 9-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 96 b Shift Shift bm Match detect an One cycle period PWREG4 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F4 PWM4 pin an bm cp INTTC4 interrupt request TMP86CH21AUG TMP86CH21AUG 9.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG3), 07D0H (TTREG3), 8002H (TC3CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC4CR), 057H (TC4CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 97 9.1 Configuration 9. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG3 (Lower byte) ? n Figure 9-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 98 Match detect Match detect Match detect mn mn PWREG4 (Upper byte) ? m Match detect Match detect TTREG3 (Lower byte) ? r TTREG4 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F4 PPG4 pin INTTC4 interrupt request TMP86CH21AUG TMP86CH21AUG 9.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 9.3.9.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz) Maximum Time Setting (TTREG4, 3 = 0100H) 7.81 ms Maximum Time Setting (TTREG4, 3 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC4: CLR SET (TC4CR).3 : (TC4CR).3 (SYSCR2).5 : Stops TC4 and 3. : SYSCR2 CLR RETI : VINTTC4: DW (SYSCR2).7 : PINTTC4 : INTTC4 vector table Page 99 9. 8-Bit TimerCounter (TC3, TC4) 9.1 Configuration TMP86CH21AUG 9.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 9-9 Setting Time in High-Frequency Warm-Up Counter Mode Minimum time (TTREG4, 3 = 0100H) 16 s Maximum time (TTREG4, 3 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC3CR), 63H (TC4CR), 05H (TTREG3), 0F800H : SYSCR2 DI SET EI SET : PINTTC4: CLR CLR CLR (SYSCR2).6 RETI : VINTTC4: DW : PINTTC4 : INTTC4 vector table Page 100 TMP86CH21AUG 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC6 interrupt request fc/2 5 fc/2 3 fc/2 7 fs fc/2 fc TC6 pin TC6M TC6S TFF6 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC6S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F6 PDO6/PWM6/ PPG6 pin TC6CK TC6CR TTREG6 PWREG6 PWM, PPG mode DecodeEN TFF6 PDO, PWM, PPG mode 16-bit mode TC5S fc/211 or fs/23 fc/2 fc/25 3 fc/2 fs 7 fc/2 fc TC5M TC5S A B C D E F G S Clear Y 8-bit up-counter Overflow 16-bit mode INTTC5 interrupt request Timer mode TC5CK TC5CR TTREG5 PWREG5 Figure 10-1 8-Bit TimerCouter 5, 6 Page 101 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG 10.2 TimerCounter Control The TimerCounter 5 is controlled by the TimerCounter 5 control register (TC5CR) and two 8-bit timer registers (TTREG5, PWREG5). TimerCounter 5 Timer Register TTREG5 (001EH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG5 (002EH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG5) setting while the timer is running. Note 2: Do not change the timer register (PWREG5) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 5 Control Register TC5CR (001AH) 7 6 5 TC5CK 4 3 TC5S 2 1 TC5M 0 (Initial value: 000 0000) NORMAL1/2, IDLE1/2 mode DV7CK = 0 000 001 TC5CK Operating clock selection [Hz] 010 011 100 101 110 111 TC5S TC5 start control 0: 1: 000: 001: TC5M TC5M operating mode select 010: 011: 1**: Operation stop and counter clear Operation start 8-bit timer Reserved Reserved 16-bit mode (Each mode is selectable with TC6M.) Reserved fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc Reserved SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC5M, TC5CK and TFF5 settings while the timer is running. Note 3: To stop the timer operation (TC5S= 1 0), do not change the TC5M and TC5CK settings. To start the timer operation (TC5S= 0 1), TC5M and TC5CK can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC6CR Page 102 TMP86CH21AUG The TimerCounter 6 is controlled by the TimerCounter 6 control register (TC6CR) and two 8-bit timer registers (TTREG6 and PWREG6). TimerCounter 6 Timer Register TTREG6 (001FH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG6 (002FH) R/ W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG6) setting while the timer is running. Note 2: Do not change the timer register (PWREG6) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 6 Control Register TC6CR (001BH) 7 TFF6 6 5 TC6CK 4 3 TC6S 2 1 TC6M 0 (Initial value: 0000 0000) TFF6 Timer F/F6 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC6 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC6CK Operating clock selection [Hz] 010 011 100 101 110 111 TC6S TC6 start control 0: 1: 000: 001: 010: TC6M TC6M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC6M, TC6CK and TFF6 settings while the timer is running. Note 3: To stop the timer operation (TC6S= 1 0), do not change the TC6M, TC6CK and TFF6 settings. To start the timer operation (TC6S= 0 1), TC6M, TC6CK and TFF6 can be programmed. Note 4: When TC6M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC6 overflow signal regardless of the TC5CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC6M, where TC5CR Page 103 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC5CR Table 10-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/2 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer Warm-up counter 16-bit PWM 16-bit PPG - - 3 fc/27 fc/25 fc/23 fs fc/2 fc TC5 pin input - - - - - - - - TC6 pin input - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - Note 1: For 16-bit operations (16-bit timer, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC5CK). Note 2: : Available source clock Table 10-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC5 pin input - - - - - - - - TC6 pin input - - - - - - - Note1: For 16-bit operations (16-bit timer, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC5CK). Note2: : Available source clock Page 104 TMP86CH21AUG Table 10-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG6, 5) 65535 256 (TTREG6, 5) 65535 2 (PWREG6, 5) 65534 1 (PWREG6, 5) < (TTREG6, 5) 65535 16-bit PPG and (PWREG6, 5) + 1 < (TTREG6, 5) Register Value Note: n = 5 to 6 Page 105 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG 10.3 Function The TimerCounter 6 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8-bit pulse width modulation (PWM) output modes. The TimerCounter 5 and 6 (TC5, 6) are cascadable to form a 16-bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 10.3.1 8-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 10-4 Source Clock for TimerCounter 5, 6 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Repeated Cycle fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter6, fc = 16.0 MHz) LD DI SET EI LD LD (TC6CR), 00010000B (TC6CR), 00011000B : Sets the operating cock to fc/27, and 8-bit timer mode. : Starts TC6. (EIRH). 4 : Enables INTTC6 interrupt. (TTREG6), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 106 TMP86CH21AUG TC6CR Internal Source Clock Counter TTREG6 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 10-2 8-Bit Timer Mode Timing Chart (TC6) 10.3.2 8-Bit Event Counter Mode (TC6) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC6CR Counter TTREG6 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 10-3 8-Bit Event Counter Mode Timing Chart (TC6) 10.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC6) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 107 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG Example :Generating 1024 Hz pulse using TC6 (fc = 16.0 MHz) Setting port LD LD LD (TTREG6), 3DH (TC6CR), 00010001B (TC6CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC6. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 108 TC6CR TC6CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Figure 10-4 8-Bit PDO Mode Timing Chart (TC6) Match detect Match detect Match detect Page 109 Counter 0 1 2 TTREG6 ? n Match detect Timer F/F6 Set F/F PDO6 pin INTTC6 interrupt request Held at the level when the timer is stopped TMP86CH21AUG 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG 10.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 10-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 110 TC6CR TC6CR Internal source clock n Write to PWREG4 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG4 PWREG6 ? Shift Shift m Match detect n m p Shift p Match detect Match detect Figure 10-5 8-Bit PWM Mode Timing Chart (TC6) Page 111 n One cycle period m Shift Shift registar ? n Match detect Timer F/F6 PWM6 pin n p INTTC6 interrupt request TMP86CH21AUG 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG 10.3.5 16-Bit Timer Mode (TC5 and 6) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 5 and 6 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected after the timer is started by setting TC6CR Note 1: In the timer mode, fix TCjCR Table 10-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC5CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRH). 4 : Enables INTTC6 interrupt. (TTREG5), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC6CR), 04H (TC6CR), 0CH TC6CR Internal source clock Counter TTREG5 (Lower byte) TTREG6 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC6 interrupt request Figure 10-6 16-Bit Timer Mode Timing Chart (TC5 and TC6) Page 112 TMP86CH21AUG 10.3.6 16-Bit Pulse Width Modulation (PWM) Output Mode (TC5 and 6) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 5 and 6 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock. When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F6 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC6 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC5 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F6 by TC6CR Note 1: In the PWM mode, program the timer register PWREG6 and 5 immediately after the INTTC6 interrupt request is generated (normally in the INTTC6 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC6 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM6 pin holds the output status when the timer is stopped. To change the output status, program TC6CR Table 10-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/2 fc/2 fc/2 fs fc/2 fc 7 5 3 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2 s fs = 32.768 kHz 16 s - - - 2s - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 fc/2 7 5 3 fs fc/2 fc 8.2 ms 4.1 ms Page 113 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG5), 07D0H (TC5CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF6 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC6CR), 056H (TC6CR), 05EH Page 114 TC6CR TC6CR Internal source clock an Write to PWREG5 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG5 FFFF 0 1 cp PWREG5 (Lower byte) ? Write to PWREG6 n m p Write to PWREG6 Figure 10-7 16-Bit PWM Mode Timing Chart (TC5 and TC6) Page 115 b Shift Shift bm Match detect an One cycle period bm PWREG6 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F6 PWM6 pin an cp INTTC6 interrupt request TMP86CH21AUG 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG 10.3.7 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC5 and 6) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 5 and 6 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock. When a match between the up-counter and the timer register (PWREG5, PWREG6) value is detected, the logic level output from the timer F/F6 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F6 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG5, TTREG6) value is detected, and the counter is cleared. The INTTC6 interrupt is generated at this time. Since the initial value can be set to the timer F/F6 by TC6CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG5), 07D0H (TTREG5), 8002H (TC5CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF6 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC6CR), 057H (TC6CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG6 pin holds the output status when the timer is stopped. To change the output status, program TC6CR Page 116 TC6CR TC6CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG5 (Lower byte) ? n Figure 10-8 16-Bit PPG Mode Timing Chart (TC5 and TC60) Page 117 Match detect Match detect Match detect mn mn PWREG6 (Upper byte) ? m Match detect Match detect TTREG5 (Lower byte) ? r TTREG6 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F6 PPG6 pin INTTC6 interrupt request TMP86CH21AUG 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG 10.3.8 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 5 and 6 are cascadable to form a 16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 10.3.8.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Maximum Time Setting (TTREG6, 5 = 0100H) 7.81 ms Maximum Time Setting (TTREG6, 5 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC6 and 5, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC6: CLR SET (TC6CR).3 : (TC6CR).3 (SYSCR2).5 : Stops TC6 and 5. : SYSCR2 CLR RETI : VINTTC6: DW (SYSCR2).7 : PINTTC6 : INTTC6 vector table Page 118 TMP86CH21AUG 10.3.8.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Minimum time (TTREG6, 5 = 0100H) 16 s Maximum time (TTREG6, 5 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC6 and 5, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC5CR), 63H (TC6CR), 05H (TTREG5), 0F800H : SYSCR2 DI SET EI SET : PINTTC6: CLR CLR CLR (SYSCR2).6 RETI : VINTTC6: DW : PINTTC6 : INTTC6 vector table Page 119 10. 8-Bit TimerCounter (TC5, TC6) 10.1 Configuration TMP86CH21AUG Page 120 TMP86CH21AUG 11. Synchronous Serial Interface (SIO) The TMP86CH21AUG has a clocked-synchronous 8-bit serial interface. Serial interface has an 8-byte transmit and receive data buffer that can automatically and continuously transfer up to 64 bits of data. Serial interface is connected to outside peripherl devices via SO, SI, SCK port. 11.1 Configuration SIO control / status register SIOSR SIOCR1 SIOCR2 CPU Control circuit Buffer control circuit Shift register Shift clock Transmit and receive data buffer (8 bytes in DBR) 7 6 5 4 3 2 1 0 SO Serial data output 8-bit transfer 4-bit transfer SI Serial data input INTSIO interrupt request Serial clock SCK Serial clock I/O Figure 11-1 Serial Interface Page 121 11. Synchronous Serial Interface (SIO) 11.2 Control TMP86CH21AUG 11.2 Control The serial interface is controlled by SIO control registers (SIOCR1/SIOCR2). The serial interface status can be determined by reading SIO status register (SIOSR). The transmit and receive data buffer is controlled by the SIOCR2 SIOCR1 (0F98H) 7 SIOS 6 SIOINH 5 4 SIOM 3 2 1 SCK 0 (Initial value: 0000 0000) SIOS Indicate transfer start / stop 0: 1: 0: 1: 000: 010: Stop Start Continuously transfer Abort transfer (Automatically cleared after abort) 8-bit transmit mode 4-bit transmit mode 8-bit transmit / receive mode 8-bit receive mode 4-bit receive mode Write only SIOINH Continue / abort transfer SIOM Transfer mode select 100: 101: 110: Except the above: Reserved NORMAL1/2, IDLE1/2 mode DV7CK = 0 000 001 SCK Serial clock select 010 011 100 101 110 111 fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 DV7CK = 1 fs/25 fc/28 fc/27 fc/26 fc/25 fc/24 Reserved External clock ( Input from SCK pin ) SLOW1/2 SLEEP1/2 mode fs/25 Write only Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz] Note 2: Set SIOS to "0" and SIOINH to "1" when setting the transfer mode or serial clock. Note 3: SIOCR1 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Control Register 2 SIOCR2 (0F99H) 7 6 5 4 WAIT 3 2 1 BUF 0 (Initial value: ***0 0000) Page 122 TMP86CH21AUG Always sets "00" except 8-bit transmit / receive mode. 00: WAIT Wait control 01: 10: 11: 000: 001: 010: BUF Number of transfer words (Buffer address in use) 011: 100: 101: 110: 111: Tf = TD(Non wait) Tf = 2TD(Wait) Tf = 4TD(Wait) Tf = 8TD (Wait) 1 word transfer 2 words transfer 3 words transfer 4 words transfer 5 words transfer 6 words transfer 7 words transfer 8 words transfer 0F90H 0F90H ~ 0F91H 0F90H ~ 0F92H 0F90H ~ 0F93H 0F90H ~ 0F94H 0F90H ~ 0F95H 0F90H ~ 0F96H 0F90H ~ 0F97H Write only Note 1: The lower 4 bits of each buffer are used during 4-bit transfers. Zeros (0) are stored to the upper 4bits when receiving. Note 2: Transmitting starts at the lowest address. Received data are also stored starting from the lowest address to the highest address. ( The first buffer address transmitted is 0F90H ). Note 3: The value to be loaded to BUF is held after transfer is completed. Note 4: SIOCR2 must be set when the serial interface is stopped (SIOF = 0). Note 5: *: Don't care Note 6: SIOCR2 is write-only register, which cannot access any of in read-modify-write instruction such as bit operate, etc. SIO Status Register SIOSR (0F99H) 7 SIOF 6 SEF 5 4 3 2 1 0 SIOF SEF Serial transfer operating status monitor Shift operating status monitor 0: 1: 0: 1: Transfer terminated Transfer in process Shift operation terminated Shift operation in process Read only Note 1: Tf; Frame time, TD; Data transfer time Note 2: After SIOS is cleared to "0", SIOF is cleared to "0" at the termination of transfer or the setting of SIOINH to "1". (output) SCK output TD Tf Figure 11-2 Frame time (Tf) and Data transfer time (TD) 11.3 Serial clock 11.3.1 Clock source Internal clock or external clock for the source clock is selected by SIOCR1 Page 123 11. Synchronous Serial Interface (SIO) 11.3 Serial clock TMP86CH21AUG 11.3.1.1 Internal clock Any of six frequencies can be selected. The serial clock is output to the outside on the SCK pin. The SCK pin goes high when transfer starts. When data writing (in the transmit mode) or reading (in the receive mode or the transmit/receive mode) cannot keep up with the serial clock rate, there is a wait function that automatically stops the serial clock and holds the next shift operation until the read/write processing is completed. Table 11-1 Serial Clock Rate NORMAL1/2, IDLE1/2 mode DV7CK = 0 SCK 000 001 010 011 100 101 110 111 Clock fc/213 fc/28 fc/27 fc/26 fc/25 fc/24 External Baud Rate 1.91 Kbps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps External Clock fs/25 fc/28 fc/27 fc/26 fc/25 fc/24 External DV7CK = 1 Baud Rate 1024 bps 61.04 Kbps 122.07 Kbps 244.14 Kbps 488.28 Kbps 976.56 Kbps External SLOW1/2, SLEEP1/2 mode Clock fs/25 External Baud Rate 1024 bps External Note: 1 Kbit = 1024 bit (fc = 16 MHz, fs = 32.768 kHz) Automatically wait function SCK pin (output) SO pin (output) Written transmit data a a0 a1 a2 a3 b b0 b1 c b2 b3 c0 c1 Figure 11-3 Automatic Wait Function (at 4-bit transmit mode) 11.3.1.2 External clock An external clock connected to the SCK pin is used as the serial clock. In this case, output latch of this port should be set to "1". To ensure shifting, a pulse width of at least 4 machine cycles is required. This pulse is needed for the shift operation to execute certainly. Actually, there is necessary processing time for interrupting, writing, and reading. The minimum pulse is determined by setting the mode and the program. Therfore, maximum transfer frequency will be 488.3K bit/sec (at fc=16MHz). SCK pin (Output) tSCKL tSCKH tcyc = 4/fc (In the NORMAL1/2, IDLE1/2 modes) 4/fs (In the SLOW1/2, SLEEP1/2 modes) tSCKL, tSCKH > 4tcyc Figure 11-4 External clock pulse width Page 124 TMP86CH21AUG 11.3.2 Shift edge The leading edge is used to transmit, and the trailing edge is used to receive. 11.3.2.1 Leading edge Transmitted data are shifted on the leading edge of the serial clock (falling edge of the SCK pin input/ output). 11.3.2.2 Trailing edge Received data are shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). SCK pin SO pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register 3210 *321 **32 ***3 (a) Leading edge SCK pin SI pin Bit 0 Bit 1 Bit 2 Bit 3 Shift register **** 0*** 10** 210* 3210 *; Don't care (b) Trailing edge Figure 11-5 Shift edge 11.4 Number of bits to transfer Either 4-bit or 8-bit serial transfer can be selected. When 4-bit serial transfer is selected, only the lower 4 bits of the transmit/receive data buffer register are used. The upper 4 bits are cleared to "0" when receiving. The data is transferred in sequence starting at the least significant bit (LSB). 11.5 Number of words to transfer Up to 8 words consisting of 4 bits of data (4-bit serial transfer) or 8 bits (8-bit serial transfer) of data can be transferred continuously. The number of words to be transferred can be selected by SIOCR2 Page 125 11. Synchronous Serial Interface (SIO) 11.6 Transfer Mode TMP86CH21AUG SCK pin SO pin a0 a1 a2 a3 INTSIO interrupt (a) 1 word transmit SCK pin SO pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (b) 3 words transmit SCK pin SI pin a0 a1 a2 a3 b0 b1 b2 b3 c0 c1 c2 c3 INTSIO interrupt (c) 3 words receive Figure 11-6 Number of words to transfer (Example: 1word = 4bit) 11.6 Transfer Mode SIOCR1 11.6.1 4-bit and 8-bit transfer modes In these modes, firstly set the SIO control register to the transmit mode, and then write first transmit data (number of transfer words to be transferred) to the data buffer registers (DBR). After the data are written, the transmission is started by setting SIOCR1 Note:Automatic waits are also canceled by writing to a DBR not being used as a transmit data buffer register; therefore, during SIO do not use such DBR for other applications. For example, when 3 words are transmitted, do not use the DBR of the remained 5 words. When an external clock is used, the data must be written to the data buffer register before shifting next data. Thus, the transfer speed is determined by the maximum delay time from the generation of the interrupt request to writing of the data to the data buffer register by the interrupt service program. The transmission is ended by clearing SIOCR1 TMP86CH21AUG SIOCR1 |